Modern electronics, such as smart phones, personal digital assistants, location based services devices, enterprise class servers, or enterprise class storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Contemporary electronics expose integrated circuits and packages to more demanding and sometimes new environmental conditions, such as cold, heat, and humidity requiring integrated circuit packages to provide robust structures.
Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new technologies while others focus on improving the existing and mature technologies. Research and development in the existing technologies may take a myriad of different directions.
One proven way to reduce cost is to use mature package technologies with existing manufacturing methods and equipments. Existing packaging technologies struggle to cost effectively meet the ever demanding thermal, reliability, and structural requirements of today's integrated circuits and packages.
Most integrated circuit devices use molded plastic epoxy as an epoxy mold compound (EMC) for protecting package. But the poor heat dissipation property of EMC sometimes leads to device malfunctions. Some integrated circuit devices are large and/or very thin such that they become susceptible to warpage. Both heat and warpage may lead to delamination of the molding compound. The encapsulation delamination may also pose other problems, such as poor performance in moisture level sensitivity (MSL) tests.
A variation of existing technologies uses mature package technologies with lead fingers made from lead frames. However, lead frame packages typically use bond wires electrically connecting the lead fingers to the integrated circuit. Another variation of existing technologies uses solder bumps on the integrated circuit with a flip chip mounting. Yet another variation combines flip chip style mounting with lead frame packages.
The lead design of integrated circuit packages, such as quad flat nonleaded (QFN) packages, generally has a lug feature to provide locking between lead and mold compound. But, it adversely reduces metal-to-metal space and disturbs mold compound flow. This impact is bigger than other types of lead frame packages due to its inherently small size of the package. As a result, it causes reliability problem such as delamination between lead, tie-bar or paddle and mold compound or internal void. When it comes to the Flip Chip packages, die area covers more space above the paddle and some portion of leads as well and the problem tends to be more serious or more frequent.
Thus, a need still remains for an integrated circuit package system providing low cost manufacturing and improved reliability for the integrated circuit package. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.